Y. Zhu et al., "A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS," IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, Jun. 2010.A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS. Zhu, Yan,Chan, Chi-Hang,Chio, U-Fat,Sin, Sai-Weng,U, Seng...
A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology Y. Zhu et al., "A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS," IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121... Q Ning,G Zhang,Y Bo,... - 《半导体学报(...
机译:90 nm CMOS的10位100-MS / s无参考SAR ADC 获取原文 获取原文并翻译|示例 获取外文期刊封面目录资料 开具论文收录证明 >> 文献代查 >> 文献数据库(团队版) >> 摘要 A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power oper...
A 10-bit 50-MS/s reference-fee low power successive approximation register (SAR) analog-to-digital converter (ADC) is presented. An energy efficient switch... Qiao,Ning,(乔宁),... - 《Journal of Semiconductors》 被引量: 60发表: 2012年 A 10-bit 100 MSamples/s BiCMOS D/A Converter Th...
A 100-MS/s reference-free SAR ADC in 90 nm CMOS[A]. 2010.乔宁,张国全,杨波,刘忠立,于芳.A 10-bit 50-MS/s reference-free low power SAR ADC in ... Q Ning,G Zhang,Y Bo,... - 《半导体学报(英文版)》 被引量: 65发表: 2012年 A low power 10 bit, 80 MS/s CMOS pipelined ADC ...
Kuroda, Split capacitor DAC mismatch calibration in successive approximation ADC. In: 2009 IEEE Custom Integrated Circuits Conference, pp. 279–282 (2009) Y. Chung, C. Yen, An 11-bit 100-ms/s subranged-SAR ADC in 65-nm cmos. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(12)...
Successive approximation register (SAR)Analog-to-digital converter (ADC)Metastability eliminationThis paper presents a fully integrated 10-bit 100 MS/s successive approximation register (SAR) ADC for the high energy physics experiments. The ADC uses a non-binary weighted capacitor digital-to-analog ...
A 10-bit 10-MS/s reference-free SAR ADC in 90nm CMOS IEEE J. Solid-State Circuits (2010) S.M.Louwsmaet al. A 1.35GS/s, 10b, 175mW time-interleaved ad converter in 0.13μm CMOS IEEE J. Solid-State Circuits (2008) B. Verbruggen, M. Iriguchi, J. Craninckx, A 1.7mW 11b 25...
This paper presents an area efficient 10-bit, 40 MS/s SAR ADC. The design strategy to minimize the circuit area adopts the pipelined architecture. The 10-bit SAR ADC is divided into 4-bit (first stage) and 6-bit (second stage) SAR ADC. The two-stage pipelined structure achieves a redu...
This brief presents a 10-bit 600 MS/s 4-channel time-interleaved (TI) successive approximation register analog-to-digital converter (ADC). A background calibration algorithm using Lagrange polynomial interpolation is introduced to calibrate timing skew. It consists of digital detection and adaptive de...