Warning (332174): Ignored filter at <filename>.sdc: <hierarchy>.gpll~PLL_OUTPUT_COUNTER|vco1ph[0] could not be matched with a pinEnvironment Bug ID: 2205795470 FPGA Intellectual Property PLL Version Found: NA Description You might see this warning in the Quartus® II software when ...
Warning (332174): Ignored filter at _p0.sdc(679): _UNDEFINED_PIN__driver_core_clk could not be matched with a clock pll_driver_core_clkis the driver clock only for the example project. If you are not using the example project, Quartus does not recognize the driver clock in the user ...