数电vhdl代码七段数码管译码器表决器半加器全加器四位串型加法器 七段数码管译码器 library ieee; use ieee.std_logic_1164.all; entity seg7_1 is port(a: in std_logic_vector(3 downto 0); b: out std_logic_vector(6 downto 0)); end entity seg7_1;...