This paper presents a continuous-time $\\\Delta\\\Sigma$ ADC in a 28nm-FDSOI CMOS technology. The ADC is clocked at 5GHz with a signal bandwidth of 250 MHz, for an oversampling ratio (OSR) of only 10. The conversion from high-level model to circuit-level implementation requires multiple...
A new method is proposed for converting any continuously running discrete-time delta-sigma modulator to a multi-channel ADC by modifying only the digital filters. The two input channels are multiplexed and fed to the modulator. The cross-talk that would exist, if the output of the decimation ...
These techniques are based on the use of \\(\\sum\\varDelta\\) streams for the stimulation of the ADC. Binary and ternary test stimuli have been proposed. In this chapter, we aim at the validation of these embedded test techniques, comparing the results obtained with the different types ...
multi-channel analog-to-digital converter (ADC)delta-sigma modulationcrosstalkequalizersA new method is presented for converting any continuously running discrete-time delta-sigma modulator (DTDSM) into a multi-channel ADC by adding only a digital filter at the output. The inputs are multiplexed ...