The storage circuits 154 of an embodiment include a 2-to-1 multiplexer 220 that couples to receive input signals comprising the write data signal W0 and a delayed write data signal W0+1.00. The multiplexer 220 receives the delayed write data signal W0+1.00 via a coupling with a first registe...
error-detection information may be synchronized using a flip-flop310-8and selectively coupled to subsequent components using the multiplexer354. An output from the multiplexer354may be synchronized using the flip-flop310-7and transmitted on the unidirectional error code link324using the transmitter312-...
(s) received from an on-chip LBIST controller. One implementation of this memory interface latch can include a multiplexer (mux) within the read path of the memory device that allows, in response to the LBIST control signal, the write data to replace output data of the memory unit. While ...
7. The controller of claim 1, wherein the write control sequencer provides signals to an error code generator. 8. The controller of claim 1, wherein the write control sequencer provides signals to a scrambler. 9. The controller of claim 1, wherein the write control sequencer provides signals...
error-detection information may be synchronized using a flip-flop310-8and selectively coupled to subsequent components using the multiplexer354. An output from the multiplexer354may be synchronized using the flip-flop310-7and transmitted on the unidirectional error code link324using the transmitter312-...
current overshoot. In this embodiment, the bit sequence as well as the length of the predetermined pattern are programmable. The operation of the programmable pattern detector92will be described with reference toFIG. 6, but it is also disclosed in the Verilog source code included in the appendix...
The memory controller includes a plurality of series-coupled delay elements to provide respective, differently-delayed internal delayed timing signals and a multiplexer to select one of the delayed timing signals to be output as the second timing signal based on a difference between the first ...
The storage circuits 154 of an embodiment include a 2-to-1 multiplexer 220 that couples to receive input signals comprising the write data signal W0 and a delayed write data signal W0+1.00. The multiplexer 220 receives the delayed write data signal W0+1.00 via a coupling with a first registe...