Digilent Nexys Video (Xilinx Artix 7 XC7A200T) Intel Stratix 10 DX dev kit (Intel Stratix 10 DX 1SD280PT2F55E1VG) Intel Stratix 10 MX dev kit (Intel Stratix 10 MX 1SM21CHU1F53E1VG) Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50) Xilinx Alveo U200 (Xilinx Virtex UltraScale+ XCU...
使用SD卡数据读写控制器读取事先存储在SD卡的图片数据,将读取的图片数据通过SDRAM数据读写控制器暂存在SDRAM芯片中,通过VGA显示器将暂存在SDRAM 的图片显示出来。 SD卡内存储图片有两张,两张图片交替显示在VGA显示器上,分辨率为640*480。 15.2.2. 硬件资源 参见“SD卡数据读写控制”、“VGA显示器驱动设计与验证...
rtl/arp.v : ARP handling logic rtl/arp_cache.v : ARP LRU cache rtl/arp_eth_rx.v : ARP frame receiver rtl/arp_eth_tx.v : ARP frame transmitter rtl/eth_arb_mux.py : Ethernet frame arbitrated multiplexer generator rtl/axis_eth_fcs.v : Ethernet FCS calculator rtl/axis_eth_fcs_64.v...
For IP and ARP support only, useip_complete(1G) orip_complete_64(10G/25G). For UDP, IP, and ARP support, useudp_complete(1G) orudp_complete_64(10G/25G). Top level gigabit and 10G/25G MAC modules areeth_mac_*, with various interfaces and with/without FIFOs. Top level 10G/25G...
This branch is 163 commits behind alexforencich/verilog-ethernet:master.Folders and files Latest commit alexforencich Force possible floating point parameter value to integer when taking … 2199a15· Nov 2, 2022 History1,039 Commits .github/workflows Set algorithm for pytest-split Jun 28, 2021...
rtl/arp.v : ARP handling logic rtl/arp_cache.v : ARP LRU cache rtl/arp_eth_rx.v : ARP frame receiver rtl/arp_eth_tx.v : ARP frame transmitter rtl/eth_arb_mux.py : Ethernet frame arbitrated multiplexer generator rtl/axis_eth_fcs.v : Ethernet FCS calculator rtl/axis_eth_fcs_64.v...