下列Verilog HDL代码描述中,采用时钟信号clock上升沿和复位信号reset下降沿触发的是( )。A.always @ ( posedge clock, neg
set_n,rst_n,q );input clk;input d;input set_n;input rst_n;output q;reg q;always@(posedge clk or negedge rst_n)begin if(!rst_n)q<= 1'b0;else if(!set_n)q<= 1'b1;else q<=d;end endmodule