PURPOSE:To make the variable phase shifting width of the title circuit wider by changing the variable capacity value of each variable capacity element of the 1st and 2nd phase shift circuits in the opposite directions by means of an external control voltage. CONSTITUTION:The emitter and collector ...
A variable phase circuit for microwave and millimeter wave applications includes a distributed-constant transmission line, a number of phase shifters respectively responsive to control signals for introducing a desired amount of phase shift to and removing the introduced phase shift from the transmission...
and7-11are schematics of the rectifier and inverter circuit for a basic 6-pulse system. For a 12-pulse system, phase shift transformers are added together with six additional thyristors. The phase shift transformers shift the output of the second set of thyristors by 30 degrees. If more pulse...
tonal components used for variable-length coding of the pitch type coding circuit; and the noise characteristic components to encode noise encoder circuit. ... 筒井京弥,园原美冬 被引量: 2发表: 2003年 Audio encoder and decoder The invention discloses an audio coder and an audio decoder. The ...
A clock generator includes a frequency divider for outputting a divided clock signal by dividing an input clock signal in accordance with a dividing ratio control signal; and a phase adjusting circuit for adjusting a phase of an internal clock signal with that of an external clock signal. The ...
摘要: PROBLEM TO BE SOLVED: To provide a variable latency circuit capable of preventing phase shift of a clock when an operation frequency is high and reducing circuit delay when the operation frequency is low.收藏 引用 批量引用 报错 分享 文库来源 其他来源 求助全文 VARIABLE LATENCY CIRCUIT AND...
Ideally, to meet the low noise, high linearity objectives of a mixer we need some circuit that implements a polarity-switching function in response to the LO input. Thus, the mixer can be reduced to Figure 4.4, which shows the RF signal being split into in-phase (0°) and anti-phase ...
which represents a maximum phasing error of less than 0.01% of the B CLOCK. The Precision Oscillator 30 has a frequency stability such that any shift in frequency which might occur during the time required to transmit a document will cause an insignificant phase shift to occur between the B ...
an i-th partial delay circuit (i is an integer not less than 3) having an output terminal, a first input terminal connected to an output terminal of an (i-1)th partial delay circuit, and a second input terminal connected to an output terminal of an (i-2)th partial delay circuit, wh...
After the analysis of the four frequency dividing control process, a transient mathematical model of two-phase and three-phase to two-phase conduction is ... Y Meng,J Chen,M Duan,... - IEEE 被引量: 0发表: 2016年 Flip-flop circuit, frequency divider and frequency dividing method In respo...