执行时候出错, [DRC REQP-1712] Input clock driver: Unsupported PLLE2_ADV connectivity. The signal u_clk_wiz_0/inst/clk_in1 on the u_clk_wiz_0/inst/plle2_adv_inst/CLKIN1 pin of u_clk_wiz_0/inst/plle2_adv_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO. ...
一、报错内容 [DRCREQP-1712]Inputclockdriver:UnsupportedPLLE2_ADVconnectivity.Thesignalclk_50m_gen/inst/clk_inontheclk_50m_gen/inst/plle2_adv_inst/CLKIN1pinofclk_50m_gen/inst/plle2_adv_instwithCOMPENSATIONmodeZHOLDmustbedrivenbyaclockcapableIO. 二、报错原因 IBUFGDSclk_inst(.O(clk),.I(clk_p...
执行时候出错, [DRC REQP-1712] Input clock driver: Unsupported PLLE2_ADV connectivity. The signal u_clk_wiz_0/inst/clk_in1 on the u_clk_wiz_0/inst/plle2_adv_inst/CLKIN1 pin of u_clk_wiz_0/inst/plle2_adv_inst... 查看原文 vivado的pll时钟约束的重命名 /plle2_adv_inst/CLKIN1] -...
一、报错内容 [DRC REQP-1712] Input clock driver: Unsupported PLLE2_ADV connectivity. The signal clk_50m_gen/inst/clk_in on the clk_50m_gen/inst/plle2_adv_inst/CLKIN1 pin of clk_50m_gen/inst/plle2_adv_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO. 二、报错...