confb |=0x5;break;caseSND_SOC_DAIFMT_RIGHT_J: confb |=0x6;break; }break;caseSNDRV_PCM_FORMAT_S18_3LE:caseSNDRV_PCM_FORMAT_S18_3BE: pr_debug("18bit\n");switch(sta32x->format) {caseSND_SOC_DAIFMT_I2S: confb |=0x8;break;caseSND_SOC_DAIFMT_LEFT_J: confb |=0x9;break;caseS...
| SND_SOC_DAIFMT_CBM_CFM);if(ret <0)returnret;/* Set the AP DAI configuration */ret =snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);if(ret <0)returnret;/* Set WM8580 to drive MCLK from its PLLA */ret = snd_soc_dai_...
McASP’s transmit and receive clocking sections are intended to operate synchronously (ASYNC=0), codec is clock and frame master (SND_SOC_DAIFMT_CBM_CFM). The problem is that with the davinci-mcasp driver implementation provided with SDK 06.03 (4.19.94-gbe5389fd85) the RX secеion is ...
regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr);/* DAI clock master masks */switch(fmt & SND_SOC_DAIFMT_MASTER_MASK) {caseSND_SOC_DAIFMT_CBM_CFM:/* codec is master */cr1 |= SAI_XCR1_SLAVE; sai->master =false;break;caseSND_SOC_DAIFMT_CBS_CFS: sai->mast...
cs4270->mode = format & SND_SOC_DAIFMT_FORMAT_MASK;break;default: dev_err(component->dev,"invalid dai format\n");return-EINVAL; }/* set master/slave audio interface */switch(format & SND_SOC_DAIFMT_MASTER_MASK) {caseSND_SOC_DAIFMT_CBS_CFS: ...
SND_SOC_DAIFMT_CBS_CFS);if(ret <0)returnret;/* set the codec system clock for DAC and ADC */ret = snd_soc_dai_set_sysclk(codec_dai, WM8750_SYSCLK, clk, SND_SOC_CLOCK_IN);if(ret <0)returnret; ret =snd_soc_dai_set_clkdiv(cpu_dai, S3C2412_DIV_RCLK, div.fs_div);if(ret...
pr_debug("24bit or 32bit\n");switch(sta32x->format) {caseSND_SOC_DAIFMT_I2S: confb |=0x0;break;caseSND_SOC_DAIFMT_LEFT_J: confb |=0x1;break;caseSND_SOC_DAIFMT_RIGHT_J: confb |=0x2;break; }break;case20: pr_debug("20bit\n");switch(sta32x->format) {caseSND_SOC_DAIFMT_I2S...