Just thought the community might be able to input some feedbacks as KNL MPSS and KNC MPSS are similar. Thread can be closed, as it is Intel confidential and this might not be the right place i can find a solution. Thank you all for your inputs. Translate 0 Kudos Copy link Reply ...
Programming at the instruction level isn't encouraged, considering the incompatibility with AVX and the pending change for the KNL. There is a fair amount of use of the MIC intrinsics which are installed with icc. As you said, you need at least 2 threads per core to fill the VPU pipeline...