Error: VVP input file 10.3 can not be run with run time version 12.0 (stable) 求助大佬,在/vsim下执行make run_test SIM=iverilog时收到上面的报错,尝试重装iverilog未能解决,应该如何解决,谢谢 京五环以外 2023-08-12 08:29:06 modelsim加载设计时出错该怎么办? 我使用核心生成器生成DDR3然后我有exam...
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