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Memtest86+ for LoongArch, this build is based on[memtest](https://github.com/memtest86plus/memtest86plus)commitID: 3f86696. This is a beta test version, it has been tested on 3A5000, 3A6000, 3C5000, 3D5000 platforms. LoongArch branch[repo](https://github.com/kilaterlee/memtest86pl...
Breadcrumbs memtest86 / smp.cTop File metadata and controls Code Blame 691 lines (584 loc) · 16.6 KB Raw /* * MemTest86+ V5 Specific code (GPL V2.0) * By Samuel DEMEULEMEESTER, sdemeule@memtest.org * http://www.canardpc.com - http://www.memtest.org * --- * smp.c - Mem...
/* * MemTest86+ V5.00 Specific code (GPL V2.0) * By Samuel DEMEULEMEESTER, sdemeule@memtest.org * http://www.canardpc.com - http://www.memtest.org */ #define AMD_INDEX_IO_PORT 0xCD6 #define AMD_DATA_IO_PORT 0xCD7 #define AMD_SMBUS_BASE_REG 0x2C #define AMD_PM_DECODE_EN...
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for (i = 0; smbcontrollers[i].vendor > 0; i++) { // check if this is a known smbus controller if (valuev == smbcontrollers[i].vendor) { pci_conf_read(0, smbdev, smbfun, 2, 2, &valued); // read the device id if (valued == smbcontrollers[i].device) { return i; } ...
Initial import from 5.01 tarball at memtest86.org 95e230d· Feb 19, 2018 HistoryHistory Breadcrumbs memtest86 / msr.hTop File metadata and controls Code Blame 145 lines (118 loc) · 3.92 KB Raw #ifndef __ASM_MSR_H #define __ASM_MSR_H /* * Access to machine-specific registers (ava...