Hi I genearate the LL10G_10GBASER_RegMode example design. then use the mac and phy in my project, but I found it often reports timing viloation
I don't know if I can help, but I'll throw out an idea and ask for some help in return. I notice that the timing violation is between two different clock domains, as you mention. Sometimes it's okay for there to be what seems to be a violation between d...