Driver Version:"" Flags:"bus master, fast devsel, latency 0, IRQ 233" I/O Ports:"Not Available" Location:"pci@0000:00:02.0" Manufacturer:"Intel Corporation [8086]" Power Management Capabilities:"Power Management version 3" Refresh Rate - Current:"59.95" Resolution:"2560x1440" - Memory Ph...
set_location_assignment PIN_R38 -to rx_serial_data[2] set_location_assignment PIN_P40 -to rx_serial_data[3] # refclkgxb* Settings - LVDS # 322.265625MHz set_location_assignment PIN_AH36 -to ref_clk_clk_1 set_instance_assignment -name IO_STANDARD LVDS -t...
Driver Version:"" Flags:"bus master, fast devsel, latency 0, IRQ 233" I/O Ports:"Not Available" Location:"pci@0000:00:02.0" Manufacturer:"Intel Corporation [8086]" Power Management Capabilities:"Power Management version 3" Refresh Rate - Current:"59.95" Resolution:"2560x1440" - ...
Sometimes it's okay for there to be what seems to be a violation between different clock domains, but the timing analyzer does not know that it's okay. Perhaps you have to tell the timing analyzer that it is okay for there to be a violation. You can do this...