In this work, the positive feedback adiabatic logic PFAL-based design for digital circuits using CMOS is proposed and compared with the conventional circuit. The design is simulated, and with the comparison of conventional CMOS 2:1 multiplexer circuit, the designed PFAL CMOS 2:1 multiplexer ...
The low voltage full adder circuit has been implemented using the new XOR, XNOR and MUX circuits. The simulation shows that the new low voltage full adder has less power dissipation and a smaller power-delay product than previous full adder circuits. 展开 ...
In this work, the idea of parallel computing for a full adder has been proposed. Based on parallel computing, a new architecture of full adder (A-I) has be
For the addition of twon-bit integers, a naive method is to useRipple Carry Adder(RCA), which is constructed by cascading multiple full adder gates, as illustrated in Fig.3. For ann-bit adder, there must benfull adder gates. The output of the full adder can be obtained by the following...
The lower four bits are used as input to a 16-to-1 MUX 1202. Thus, once the word has been fetched the desired bit is selected using the lower four bits of k(B,j). In a preferred embodiment, the data memory is common with the rest of the system, and provisions must be made ...
By usingthis 2T (EX-NOR and 2:1 MUX) A gate the size of the fulladder has been reduced to a large extent which can beimplemented with only 6 transistors and applied this designin 4:2 compressor. The proposed full adder has a significantimprovement in silicon area and power delay product...
In this paper a hybrid design of Full adder which generates the high logic outputs is proposed. The Full adder is design with GDI method which gives a high Swing outputs and consumes less area in 0.18 CMOS technology.JANARDAN REDDY GUNDAM...
Design of Array Multiplier using Mux Based Full Adderdoi:10.17577/IJERTV6IS050599Jyothi KamatamKumaraswamy GajulaIJERT-International Journal of Engineering Research & Technology
In the recent past there is a rapid development in the field of digital technology especially in signal processing and image processing based applications Excellent performance high speed, compactable in size low power and less delay are the essential needs of the devices used for applications such...
The proposed method uses full adder based design of 2 - Bit Magnitude Comparator. The Full adder is designed using two methods: The First method uses two XNOR gates and one MUX and the second method uses 9T full adder design. The proposed method design demonstrates its superiority against ...