A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner一种10Gb/s具有周期性相位校准双沿触发CDR和CTLE/DFE组合均衡功能的接收端serial linkreceiverCDRequalizer本文提出了65纳米CMOS工艺下的一种10Gb/s 低功耗的有线电互连接收端.接收端的面积为300μm×500μm.通过集成新的周期性...
7, the phase of CLK is adjusted by a clock-and-data recovery (CDR) circuit or some other mechanism so that the input data bits are sampled at the center of the eye. The phase of the CLK signal driving the select of the MUX is chosen so that DFR is delayed by one UI relative to...