charge pumpphase-locked-loop (PLL)This work proposed a high-performance charge-pump circuit for phase-locked-loop (PLL) applications. The proposed charge-pump circuit is composed of a pair of wide-swing current mirror and symmetric pump circuits which can provide ride output range and have no ...
lecture notes in engineering & computer scienceJianbin Pan, Yuanfu Zhao, "Design of a Charge-Pump PLL for LVDS SerDes" International multi conference of Engineers and Computers Scientists, Vol. II, March 2010.Jianbin Pan, Yuanfu Zhao, Design of a Charge-Pump PLL for LVDS SerDes, in proc. ...
This work proposed a high-performance chargepump circuit for phase-locked-loop (PLL) applications. The proposed charge-pump circuit is composed of a pair of wide-swing current mirror and symmetric pump circuits which can provide wide output range and have no jump phenomenon. The proposed charge-...
A low-off-leakage-current charge pump is used for open-loop FSK modulation. When the PLL is in open loop mode, the frequency drift of the output ... A Yamagishi,M Ugajin,T Tsukahara - International Microwave Symposium Digest 被引量: 36发表: 2003年 Design of high performance CMOS charge ...
Design and Analysis of Charge Pump for PLL Applications using 70nm TechnologyDEEPSHIKHA MITTALVIRENDRA VERMA
The charge pump proposed in this paper has two complementary differential pairs for the UP and Down signals. Providing equal values for I UP and I Down the current matching is less of an issue for the new charge pump. Indeed, the simulation results show that the proposed charge pump ...
Deep submicron CMOS technologies offer the high speed and low power dissipation required in multigigahertz communication systems such as optical data links... Razavi,B.,Lee,... - Solid-State Circuits, IEEE Journal of 被引量: 259发表: 1995年 The design of a differential CMOS charge pump for ...
This high frequency, low-phase-noise clock is a combination of a high frequency voltage-controlled oscillator (U1), a phase-locked loop (U2), and a crystal oscillator (U3) as shown in Figure 2. Figure 1. Typical high-speed data converter system using the MAX104 ADC and a PLL-based...
Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today’s devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalabil...
Charge pump generates pulses for loop filter. Reference frequency 0.32…10 MHz. Output current is 41...142.5 uA. The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology. View PLL ECL phase-frequency detector with ECL charge pump full description to... see the entire PLL...