The proposed algorithm can stop the turbo decoder earlier than traditional methods in both high SNR and low SNR environment. Finally, for verifying the proposed algorithm, a turbo decoder using new phase estimation is designed with TSMC 0.18μm 1P6M process, the chip size is 1530μm 1504μm...
This article describes the development of current DAB receivers, with special emphasis on the design of the digital signal processor–based channel decoder which has been used in the 3rd–generation Eureka receivers, as well as a prototype decoder based on an application– specific chip–set. 展开...
[translate] aA Novel Design of CAVLC Decoder with Low Power and High Throughput Considerations CAVLC译码器一个新颖的设计以低功率和高生产量考虑 [translate] 英语翻译 日语翻译 韩语翻译 德语翻译 法语翻译 俄语翻译 阿拉伯语翻译 西班牙语翻译 葡萄牙语翻译 意大利语翻译 荷兰语翻译 瑞典语翻译 希腊语翻译 ...
aA decoder is possible of producing more than 1 outputs at a moment with special design 译码器是可能的导致超过1产品在片刻以特别设计[translate]
Examples of this include a Clock Generation Unit, whose configuration depends on the types of clocks required by all IP, and an address decoder for a system interconnect bus, whose configuration depends on the register address mapping of each IP. We make all this IP configuration information ...
The high-throughput 3GPP Advance Turbo code requires turbo decoder architecture. Interleaver is known to be the main obstacle to the decoder implementation and introduces latency, due to the collisions it introduces in accesses to memory. In this paper, we propose a low-complexity soft Input Soft...
This paper presents the design of a VLSI implementation of a real-time video decoder. The video decoder can decode a motion CIF format video sequence from a data rate of 5 kbyte/frame at 30 frames/sec with a signal-to-noise ratio of 32 dB. It is found that the real-time decoder has...
This paper presents an implementation of hardware/software co-design for high efficiency advanced-audio-coding (HE-AAC) audio decoder. The decoder system is partitioned into software and hardware part throughout the computation analysis. In our design strategy, the bitstream parser and lower complexit...
Thus this paper proposes a fast algorithm adapted for run_before decoder and the parallel architecture for level decoder, to improve the decoding performance. According to the features of these two methods, we name these two new methods as MLD (Multiple Level Decoding) and NZS (Non-Zero ...
The resulting baseline hardware design decodes 62 Mbins/s and achieves a 10× speed-up compared to an optimized software decoder for a typical workload at only a tenth of the processors clock frequency. The pipelined design gives an additional 13.5%, while the parallel design provides a 10%...