用verilog设计一个3-8译码器+要求分别用case语句和if_else语句

2024-12-02 10:18:30

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...8译码器~(要求分别用case语句和if_else语句各写一份~) - 百度知道

begin if(code[2])if(code[1])if(code[0])result = 8'h80;else result = 8'h40;else if(code[0])result = 8'h20;else result = 8'h10;else else if(code[1])if(code[0])result = 8'h08;else result = 8'h04;else if(code[0])result = 8'h02;else result = 8'h01;els...
...8译码器~(要求分别用case语句和if_case语句各写一份~) - 百度知道

else if(code[1])if(code[0])result = 8'h08;else result = 8'h04;else if(code[0])result = 8'h02;else result = 8'h01;else end endmodule